1. Field
This disclosure relates to fabrication of semiconductor wafers and, more specifically, to semiconductor wafers made of silicon carbide.
2. Related Arts
The semiconductor chip industry owes much of its success to the natural properties of silicon. These properties include the ease of growing native oxide (SiO2), the excellent insulating properties of its native oxide, and the relative ease of fabrication of silicon wafers and devices within the silicon wafers. For example, silicon and its native oxide are easily etched using either wet or dry plasma etch processes. Consequently, many processes have been developed for fabrication of highly pure (99.9999999% pure), monocrystalline, and relatively large (300 mm, with preparation underway for 450 mm) silicon wafers. Silicon wafers are the primary material used in the fabrication of chips for computing and power electronics.
Other materials, such as, e.g., Sapphire, GaN (Gallium Nitride), AlN (Aluminum Nitride) and SiC (silicon carbide), exhibit properties useful in fabrication of semiconductor devices such as detectors, light emitters and power devices; however, to date their adoption in main-stream fabrication has been hampered due to the difficulties in their fabrication. Generally, standard silicon processes cannot be implemented when working with these other semiconductor materials. For example, while pure monocrystalline silicon can be easily grown using the Czochralski growth method, such a growth method cannot be used for growing SiC. Instead, a high temperature sublimation method must be employed. Similarly, since SiC cannot be easily etched, standard silicon wafering techniques cannot be easily employed for wafering SiC.
On the other hand, high-temperature/high-voltage semiconductor electronics can benefit from the natural properties of SiC. For example, SiC is used for ultrafast, high-voltage Schottky diodes, MOSFETs and high-temperature thyristors for high-power switching, and high power LEDs. Therefore, increasing the availability of SiC can contribute to the development of such semiconductor devices. For example, current production of 100 mm SiC wafers lags far behind the standard 300 mm silicon wafer.
Additionally, in single crystal silicon carbide, complex doping profiles in transistors and diodes cannot be reliably formed by diffusion. Complex geometrical doping configurations must be accomplished using ion implantation thru micron/submicron geometry masks formed using stepper-based photolithographic methods. In order to realize the required implantation for the targeted dopant incorporation within the semiconductor, flat substrates must be used in the photolithographic process, especially as the geometric size of the device increases.
Generally, semiconductor substrates are characterized by several metrics when being assessed for flatness and roughness. These metrics include bow, warp, total thickness variation (TTV or Global Backside Indicated Reading—GBIR), local thickness variation (LTV or Site Backsurface-referenced Ideal Plane/Range—SBIR), and site front side least squares focal plane range (site flatness quality requirements—SFQR). (for definitions and calculations see, e.g., SEMI M1-1103, ASTM F657, ASTM F1390, ASTM F1530).
In addition to being flat, the substrates must also be smooth and free of mechanical damage on the surface. This requirement is mandatory, as part of the device fabrication process the substrate will be placed into a chemical vapor deposition epitaxy process, which is used to grow crystalline thin films. As the thin film grows, it replicates the crystal structure presented on the substrate's surface. Consequently, excessive roughness and mechanical damage on the substrate's surface would result in poor film quality.
The most common methods of producing flat and smooth substrates involve a sequential series of material cutting steps to gradually achieve a high level of flatness and low roughness. Each polishing step uses smaller and smaller abrasive particles to reduce the surface roughness to the target. Polishing pads with strategically chosen mechanical properties are chosen to control the “planarization length” which influences the final waviness of the substrate and achieve the local flatness objectives.
For example, in silicon substrate processing, wafers are sliced and then treated with a lapping or grinding process to make each face of the substrate parallel, achieving global flatness. But these processes result in a significant amount of mechanical damage to the surfaces of the substrate and can result in increased bow or warp of the substrate. To remove the damage, the silicon wafers are typically immersed in a chemical solution which is used to etch the surface damage. This process, generally referred to as saw damage removal, can render the substrate surface quite wavy, and subsequent flattening processes must be applied. Next, to bring the substrate to the targeted thickness range, a series of procedures known as stock removal are applied. In silicon processing, stock removal includes one or several polishing steps using chemical mechanical polishing processes which are used to efficiently reduce the thickness of the substrate to near the target thickness and reduce waviness. Next the wafer is further polished with finer abrasive chemical mechanical polishing processes, long planarization length polishing pads and with small removal targets, in order to achieve the required flatness and roughness specifications. While there are many steps, the duration of the process from lapping/grinding to completion is only several hours, and it can deliver silicon wafers having the flatness and roughness performance required to meet lithography targets, even after CVD (chemical vapor deposition) epitaxy layers are applied to the substrate.
Several publications describe methods to polish silicon wafers to achieve control of both global and local flatness. Most common among these methods for silicon wafers is a series of slicing, edge chamfering, lapping or grinding, etching, polishing, where the polishing steps are single or double side polishing—or both types used sequentially. Double side polishing is described in U.S. Pat. No. 3,691,694. U.S. Pat. No. 6,583,050 details methods used to achieve control of silicon wafer flatness which employ double side polishing.
However, due to its nature as a hard and chemically resistant material, cutting, grinding and polishing methods for single crystal SiC resort to use of diamond and metal carbide abrasives for the primary shaping of the substrates. The chemical properties of SiC are such that it is not practical to etch the substrate to remove gross cutting related surface damage. When silicon wafers are polished, methods of chemical mechanical polishing are used and the removal of material is very efficient since the polishing chemistry can oxides etch and abrade the wafer at the same time. It is not practical to employ chemical enhanced mechanical polishing on SiC since the chemical reaction rates are very slow and the costs associated with the process become very high.
The diamond abrasives required to process SiC are very costly compared to the standard abrasives that are used to polish silicon substrates. The SiC polishing times are quite long even with diamond abrasives—the material removal rates for SiC are 5-20 times slower than the corresponding silicon substrate process. In fact, SiC is the abrasive material used to cut and polish silicon wafers. Inefficient removal rates and expensive abrasives make the process to polish SiC extremely costly, especially when conventional strategies to produce flat wafers are applied to SiC.
In order to meet the commercial and economic requirements for acceptance of SiC semiconductor devices, innovative methods to polish SiC substrates must be developed. Efficient methods of cutting and polishing SiC substrates with minimum use of abrasives and minimum intermediate steps must be realized. The polishing process duration must be practical for high volume manufacturing. The overall performance of the polishing strategy must also achieve the wafer surface crystal quality benefits (smooth and free of damage) that would normally be obtained by bulk chemical etch procedures like that used in silicon polishing. Finally the polished substrate must be suitable for epitaxy processes and the final substrate with epitaxy layer must meet the flatness requirements associated with the photolithography steps needed in the fabrication of the electrical device.
U.S. Pat. No. 8,436,366 describes a method to prepare SiC wafers that will result in control of the wafer global flatness during epitaxy and device fabrication. The method consists of slicing the SiC wafer followed by double-side grinding to adjust the flatness, double-side lapping with diamond slurry to reduce the roughness, double-side mechanical polishing with diamond slurry to further reduce the roughness and single side chemical mechanical polishing. The method states a sequence of steps targeted to control the bow and warp of the wafer, but does not detail the interplay between the steps which impact the wafer flatness parameter or the impact of each step on the final wafer shape, only double-side processing is cited as the key element. The method does not disclose means to control local flatness metrics or resulting performance of local flatness/thickness metrics. With the inclusion of many different material removal steps the result will be high manufacturing costs. This polished wafer is designed to have a flatness performance that is offset that is to compensate for undesirable bending of the wafer which can occur during the steps to manufacture a semiconductor device.
The unexpected result of the present invention is that a silicon carbide wafer can be polished with good global AND local flatness and thickness using a simple method. The method requires a lapping OR sequential two side grinding step to establish a low value global and local flatness, and to set the thickness, and a double side polish step to reduce roughness to an acceptable value. A key feature of this invention is the use of large diameter lapping and polishing equipment to simultaneously control and maintain both local and global flatness. Wafer etching is not required to achieve flatness or thickness control, nor is it necessary to use etching to remove mechanical damage. Both the global and local flatness performance achieved on the polished wafer of this invention can be maintained following chemical mechanical polish steps used to reduce the RMS roughness to small values and alternatively, after a gas phase etch is performed and SiC epitaxy film layer is applied to the surface of the polished wafer. As a result of the polished wafer manufacturing strategy, the final epitaxy wafer has favorable global and local flatness performance which will result in better utility to manufacture semiconductor devices with large active area.